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Brian J. d'Auriol and Virendra C. Bhavsar, "Multicomputer Implementations of Systolic Computations: A Unified Approach", Proc. of the 10th Annual International Conference on High Performance Computers (HPCS'96), Ottawa, Ontario, Canada, 5-7 June, 1996, published on CD-ROM by IEEE Canada Electronic Services, distributed by Carleton University Press.
We propose a unified approach for implementing systolic computations on distributed memory multicomputers (DMMCs). Advantages of this approach include its applicability to a wide range of systolic algorithms, DMMCs and computer languages. It also incorporates the evaluation of expected execution times for different possible implementations of a given systolic computation and the generation of source code for a selected implementation. We present the details of the various stages of the unified approach including the generation of a systolic array, several partitioning schemes and related theorems, source code generation, execution time analysis and optimization based on performance models. The intended use of the approach is for building a compiler that would accept a systolic algorithm specification as input and would generate an efficient executable object program.
Full Paper (pdf: 232KB)